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DLD Test on 4th October. Revise this for it !!!



Digital logic design

 

B.E.3rd sem CO                                                   Exam Date:04/10/2013

 

1.         Show how a full-adder can be converted to a full-subtractor with the addition of one inverter circuit.
2.          Design a combinational circuit with four input lines that represent a decimal digit in BCD and four output lines that generate the 9’s complement of the input digit.
3.         Construct 4x16 decoder with two 3x8 decoders
4.         Explain PLA with necessary diagrams.
5.         Explain half and full adders in detail
6.         Design and implement BCD to excess 3 code converter using minimum number of NAND gates
7.      Explain a 4 to 1 line multiplexer in detail.
8.      Design a 4 bit binary to BCD code converter
9.         Design a full adder circuit using decoder and multiplexer
10.     Define: [1] Comparator [2] Encoder [3] Decoder [4] Multiplexer [5] De-multiplexer [6] PLA
11.     Design a combinational circuit whose input is four bit binary number and output is the 2’s complement of the input binary number.
12.    Design a full-adder with two half-adders and an OR gate.
13.    Design a BCD to decimal decoder
14.    What is multiplexer? Implement the following function with a multiplexer:
F(A,B,C,D) = Σ(0 , 1 , 3 , 4 , 8 , 9 ,15 )
15.  Write short note on : Read Only Memory (ROM)
16.  A combinational circuit is defined by functions:F1(A,B,C) = Σ( 3 , 5 , 6, 7 ) & F2(A,B,C) = Σ( 0 , 2 , 4, 7 )
Implement the circuit with PLA having three inputs ,four product term and two outputs.
17.    Design an adder/subtractor circuit with one selection variable S and two inputs A and B .when S = 0 circuit performs A+B, when S = 1 circuit performs A – B by taking the 2’s complement of B
18.    Design the Combinational Circuits for Binary to Gray Code Conversion.
19.    Construct 4*16 Decoder with help of 2*4 Decoder.
20.      Discuss 4 bit BCD Adder in Detain.
21.     Explain Design Procedure for Combinational Circuit
22.    Explain 4 bit Magnitude Comparator.
23.     Explain common cathode types seven segments displays
24.     Explain 3-to-8 line decoder with diagram and truth table
25.     Design a combinational circuit that accepts a three bit binary number and generates an output binary number equal to the square of the input number.
26.     Simplify the following Boolean function using tabulation Method &  implement with nand gates.
a.       F(w,x,y,z ) = Σ( 1,4 ,6,7 , 8 ,9, 10 ,11,,15 )
b.      F(A,B,C,D,E)  = Σ(0,1,4,5,16,17,21,25,29)
c.       F=  ABCE + ABCD +BDE + BC D
27.      Determine the Prime Implicants of following Boolean Function using Tabulation Method.
F(A,B,C,D,E,F,G)=Σ(20,28,38,39,52,60,102,103,127)
28.    Define : Integrated Circuit and briefly explain SSI, MSI, LSI and VLSI, Propagation delay, fan out, noise margin, fan in, power dissipation
29.    Give Advantages & disadvantages of ICs.
30.    Give classification of Logic Families and compare CMOS and TTL families
 
 

 
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